The present invention pertains to apparatus and methods for surface planarization of metal surfaces. More specifically, it relates to electropolishing technology for planarizing metal surfaces.
In the fabrication of integrated circuits, as the number of levels in an interconnect technology is increased, the stacking of additional layers on top of one another produces a more and more rugged topography. Compounding this problem, electroplating bath additives are now more commonly utilized to aid in the rapid xe2x80x9cbottom-upxe2x80x9d filling of higher aspect ratio features (e.g. in Damascene copper electroplating processes) to ensure homogeneous metal fill of narrow features. Baths with xe2x80x9cbottom-upxe2x80x9d filling characteristics fill smaller features much more rapidly than baths without such additives. In some cases (e.g. plating baths with superior bottom-up filling characteristic and no leveling additives) plating occurs at an accelerated rate after completing the small feature filling stage. When many high aspect ratio features are located in close proximity, a macroscopic raised area (series of bumps or a raised plateau) can be formed. This bump formation is also termed, xe2x80x9cfeature overplating.xe2x80x9d
Thus, use of advanced xe2x80x9cbottom upxe2x80x9d electrofill paradigms in combination with wafers having many low and high aspect features have created a problem of deposited metal surfaces having a range of topography to be planarized that is unusually large, i.e. containing both recessed and raised areas. Commonly, features that vary in size by two orders of magnitude on a single layer exist. A 1 xcexcm deep feature can have widths of from 0.2 xcexcm to 100 xcexcm. Therefore, while electroplating is a preferred method of metalization, various aspects of improved plating regimens create challenging topography for subsequent planarization. Without planarization, the microscopic canyons that result on the integrated circuit surface from stacking of device features create a topography that (1) would limit the resolution of photo-lithography and creation of dense feature patterns, and (2) would lead to defects in the integrated circuit that would make the circuit unusable.
One method of planarization used in the art is chemical mechanical polishing (CMP). CMP is a process that uses a mixture of abrasives and pads to polish the surface of the integrated circuit. Unfortunately, CMP polishing techniques are difficult to control; the endpoint can be difficult to detect. They are also expensive. The high equipment cost, waste handling cost, and low throughput contribute to the overall expense of CMP. Also, with the introduction of low-k dielectrics into chip production, modification of traditional CMP processes will be required, as current methods result in cracking and delamination of most low-k materials, which have a very low compression strength, and are extremely fragile.
Another method of planarization involves electrolytic etching technique such as electropolishing or electroless etching. These techniques are low cost methods, relative to CMP. Lower capital cost, easier waste handling, and much higher processing rates make them desirable alternatives to CMP. Electropolishing is a method of polishing metal surfaces by applying an electric current through an electrolytic bath, and removing metal via electrolytic dissolution. The process may be viewed as the reverse of electroplating.
A problem arises during the electropolishing of surfaces in which a large number of low aspect ratio (larger width than depth) features exist. Wide interconnect lines (trenches cut in a dielectric layer for a damascene process) and contact/bond pads often have low aspect ratios. Low aspect ratio features generally require the plating of an overburden layer slightly thicker than the thickness of the Damascene layer so that the feature will be completely filled after planarization. The metal fill profile above these features exhibits large recesses having profiles which resemble the original (low aspect ratio) feature. The metallization processes used to deposit the metal, which are substantially conformal over such low aspect ratio features, are typically not continued to a point which would geometrically xe2x80x9cclosexe2x80x9d such recesses, because to do so would require depositing a very thick metal layer. To do so would be uneconomical due to necessary removal of the large excess of metal at a later stage. Conventional electropolishing techniques can planarize a surface in which the recessed feature to be planarized is no more than perhaps three times as wide as it is deep. For features wider than these, the rate of removal is essentially uniform everywhere. When the metal layer is electropolished to the dielectric surface, recesses over low aspect ratio features are propagated and expanded to produce recesses that span the width of these features leaving effectively little or no metal in the pad regions. Obviously, this is an unacceptable result.
Reid (U.S. patent application Ser. No. 09/758,307 filed Jan. 9, 2001) describes a method of electrochemical planarization of metal surfaces in which planarization rates are modulated by tight control of the distance between a metal layer to be planarized and a planar cathode (in conjunction with a highly resistive electrolyte). Mayer et al. (U.S. patent application Ser. No. 09/412,837, filed Oct. 5, 1999) describe a method of planarization of metal layers in which a xe2x80x9cpadxe2x80x9d is used to create localized fluid agitation (and/or physical contact) in raised regions relative to recessed regions to facilitate planarization. Although these inventions address the need for improved electroplanarization in semiconductor fabrication, with the demand for increasingly smaller device features, additional methods and apparatus for metal planarization would be desirable. In particular, it would be desirable to have methods and apparatus that more specifically address non-uniform electropolishing in localized areas of a wafer relative to global planarization.
What is needed therefore is improved electropolishing technology for planarizing conductive layers having varying topography, particularly metal layers having both recesses and raised regions having both very narrow (submicron) and very wide (on the order of 100 micron) widths.
The present invention pertains to apparatus and methods for electroplanarization of metal surfaces having both recessed and raised features, over a large range of feature sizes. The invention accomplishes this by use of a xe2x80x9creclaim cathodexe2x80x9d together with a flexible planar cathode and a spacing pad thereon. During electroplanarization, the flexible planar cathode conforms to the global contour of the work piece (e.g. a wafer) while the spacingpad conforms to local topography of the metal layer being planarized. In this way, dishing is reduced in the final planarized metal layer. The reclaim cathode serves as a counter electrode to the metal workpiece (anode). Therefore, most of the cathodic Faradaic reaction takes place at the reclaim electrode. To a lesser degree, the flexible cathode may undergo some Faradaic reaction.
One aspect of the invention is an electroplanarizing apparatus for removing a portion of a metal layer disposed on a wafer work surface. Such apparatus may be characterized by the following features: a wafer holder for holding the wafer such that the metal layer is exposed, the wafer holder configured to supply an anodic electrical current to the metal layer; a flexible planar cathode having a spacing pad on its surface; a movement assembly configured to position the wafer work surface and the flexible planar cathode into close proximity with each other, whereby at least a pre-defined separation distance between the flexible planar cathode and wafer work surface can be maintained throughout an electroplanarization process; an electrolyte delivery mechanism configured to provide an electrolyte to the spacing pad while the wafer is in contact with the spacing pad; and a mechanism for applying a substantially uniform force per unit area to the back side of the flexible planar cathode, thereby compressing the spacing pad between the flexible planar cathode and the wafer work surface. Many embodiments also include a reclaim cathode physically separated from the flexible cathode and serving as a primary counter electrode to the wafer. Preferably during the electroplanarization process, electrical current passes between the metal layer and the reclaim cathode, primarily, and between the metal layer and the flexible planar cathode, secondarily. Ionic current will normally flow through at least that portion of the electrolyte contained in the spacing pad.
Preferably the movement assembly further includes a mechanism for creating a lateral relative movement between the wafer work surface and the spacing pad work surface. Also preferably, the lateral relative movement between the wafer work surface and the spacing pad work surface includes at least one of (a) rotating the wafer, the flexible planar cathode, or both about an axis substantially perpendicular to the wafer work surface, (b) moving the wafer, the flexible planar cathode, or both via linear movements along one or more axes substantially parallel to the wafer work surface, (c) orbiting the wafer, the flexible planar cathode, or both substantially parallel to the wafer work surface; and (d) combinations thereof.
Preferably the mechanism for applying a substantially uniform force per unit area to the back side of the flexible planar cathode applies a force of between about 0.2 and 2 psi, more preferably less than 1 psi. Preferably the mechanism for applying a substantially uniform force per unit area to the back side of the flexible planar cathode includes at least one of (a) a fluid pressure differential in the electrolyte due to restricted flow of the electrolyte from the back side of the flexible planar cathode through the porous matrix and the spacing pad, and (b) a compressive material contacting the back side of the flexible planar cathode.
Another aspect of the invention is a flexible planar cathode assembly for electroplanarizing a metal layer disposed on a wafer work surface. Such a cathode assembly may be characterized by the following features: (a) a flexible electrode (e.g., a flexible substrate coated with a conductive material), the flexible electrode having a substantially planar front side surface; and (b) a spacing pad affixed to the substantially planar front side surface of the flexible electrode. Preferably the flexible electrode is between about 15 and 300 xcexcm thick. Also preferably the flexible electrode is made of at least one of silicon, polyimide, Kapton, polyurethane, polyethylene (Mylar), mica, and polycarbonate. Or the substrate can be omitted leaving just a thin metal electrode. Alternatively the flexible electrode could be a strong metal such as stainless steel, molybdenum, tungsten, tantalum, or a nickel-based alloy such as Hastelloy(copyright) C-22, Monel(copyright) or Inconel(copyright) which has been coated (e.g. by electroplating or sputtering or chemical vapor deposition) with an electrochemically suitable metal. In the embodiment where the flexible electrode comprises a flexible substrate with a conductive material thereon, the conductive material preferably includes at least one of platinum, copper, gold, palladium, ruthenium, various platinum-rhodium or platinum-iridium alloys. In general metal should be higher on the electrochemical series than copper (or should be copper). In some embodiments, the flexible planar cathode includes a porous matrix configured to allow electrolyte to flow through it.
Spacing pads of the invention will be chemically compatible with the electrolyte (i.e. will not dissolve or otherwise break down). The pad will have a small pore size and be sufficiently porous to allow fluid and electrical current to easily flow through. A long-lived pad is also desirable, i.e. one that wears slowly. The spacing pad is generally a non-abrasive pad. In certain specific embodiments, the spacing pad is made of at least one of a perfluoroalkoxy material, urethane material and polyvinyl alcohol (PVA). Preferably the spacing pad will include a plurality of pores having a mean diameter of between about 0.02 xcexcm and 10 xcexcm. Whatever the porous nature of the pad, preferably the spacing pad has a void volume of between about 20 and 80 percent. Generally the pad will be thin. Preferably the spacing pad, when uncompressed, is at least about three times as thick as the largest variation in height between a plurality of recessed regions and raised regions in the metal layer disposed on the wafer work surface. In a specific embodiment, the spacing pad is between about 3 and 20 microns thick.
Also preferably, the flexible electrode and the spacing pad are made of materials and configured such that, during an electroplanarization process in which a substantially uniform force per unit area is applied to the back side of the flexible electrode, the spacing pad conforms to local surface contours in the metal layer arising from a plurality of recessed and raised regions in the metal layer, while the flexible electrode conforms only to the global contour of the wafer.
Yet another aspect of the invention is a method of electroplanarizing a metal layer disposed on a wafer work surface, the metal layer having a plurality of recessed and raised regions. Such methods may be characterized by the following sequence: positioning the wafer work surface and a flexible planar cathode into close proximity with each other, the flexible planar cathode including a spacing pad on its work surface, the spacing pad and the metal layer contacting each other; applying a substantially uniform force per unit area to the back side of the flexible planar cathode, thereby compressing the spacing pad between the flexible planar cathode and the metal layer; passing an ionic electrical current from the metal layer, through an electrolyte solution contained at least in the spacing pad, and to the reclaim cathode, as well as the flexible planar cathode, such that the metal is electrolytically removed from the surface of the metal layer; and stopping the passage of current at a point where all or a majority of the metal layer is removed from the field of the wafer work surface. In some embodiements, such methods will further include substantially maintaining a pre-defined separation distance between the flexible planar cathode and the wafer work surface during electroplanarization. Also, such methods preferably further include creating a relative movement between the wafer work surface and the spacing pad before and during electroplanarization. Preferably the result of such methods is that dishing, across any region of the metal layer surface greater than 20 xcexcm in diameter, is less than 100 nanometers deep, more preferably less than 50 nanometers deep. Also preferably such methods will further include recycling the electrolyte during electroplanarization.
These and other features and advantages of the present invention will be described in more detail below with reference to the associated drawings.